Field of the Invention
The present invention relates to a frequency multiplying circuit. The frequency multiplying circuit according to the present invention can be applied, for example, to read signal generation in a disc controller used such as that for a floppy-disc used in a personal computer.
Description of the Related Art
In general, digital data with FM type modulation, modified FM type modulation (MFM type) and the like, stored in a disc memory as of a computer, is reproduced by a reproducing device having a phase locked loop circuit, a frequency multiplying circuit, and a data reading circuit.
The phase locked loop circuit extracts a clock signal from the reproduced signal. The frequency multiplying circuit multiplies the extracted clock signal by two. The frequency multiplied signal is then supplied as a data read clock signal to the data reading circuit. The data reading circuit reads the clock bits and data bits from the reproduced signal by using the data read clock signal.
Usually, in frequency multiplier circuits used for disc controllers, the oscillation frequency of the phase locked loop circuit is subject to considerable change by a lock-in process with regard to a regenerative signal, the frequency of the produced clock signal is also subject to considerable change. As the frequency of the clock signal increases, the lengths of LOW potential level periods become quite short, causing the frequency of the output signal to be considerably high. This high frequency of the output signal will cause an abnormal operation of the data reading circuit, and prevent a data reading circuit from normal operation.
Accordingly, problems have occurred in that the clock bits and data bits cannot be read, and that an error signal indicating an error in data reading cannot be generated.